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doc. version : 6 total pages : 21 date : 200 2 . 12 . 09 note: the content of this specification is subject to change. ? 2002 au optronics all rights reserved, do not copy. model name: A015AN02 product specification 1.5 ?a color tft - lcd module < >preliminary specification < ?? > final specification www.datasheet.co.kr datasheet pdf - http://www..net/
record of revision version revise date page content 0 25/dec./2001 first draft. 1 10/apr./2002 fpc length revised 5 normal mode: (u/d,shl): (h,h) ? (l,h) reverse mode: (u/d,shl): (l,l) ? (h,l) 6 v glac : 5.6(typ) ? 5.2(typ) v gl_h : - 8.1(min). - 9.0(typ), - 9.9(max) ? - 8.1(min), - 7.1(typ), - 6.1(max) v cac : 5.6(typ) ? 5.2(typ) i gh : 0.3(typ) ma (v gh =15v) ? 0.13(typ) ma (v gh =17v) i gl : - 0.6(typ ) ma (v gh = - 10v) ? - 0.19(typ) ma (v gl = - 8v) i cc : 0.8(typ), 2(max) ma ? 2(typ), 4(max) ma i dd : 1.5(typ), 2(max) ma ? 1.15(typ), 2(max) ma 8 y: 0.30(min) ? 0.29(min) 9 vertical display start: 15 ? 25 11 revised the packing form drawing mechic al drawing revised 2 09/may/2002 dc - dc converter, i/o equivalent circuit 13 revised packing form 3 31/may/2002 3 surface treatment: hard coating(3h) 7 v cac ,v gl - ac : 5.2v ? 5.6v 8 dc - dc block output voltage: 13v ? 13.5 v; vref: 1.25v ? 1 .2v 12 add fp c reliability test item 13 update outline drawing 21 updated application circuit 4 03/sep/2002 14 change package to 420 pcs/box 5 12/sep/2002 7 add led current min and max value 6 09/dec/2002 7 remove led typical voltage and add le d maximum voltage www.datasheet.co.kr datasheet pdf - http://www..net/
version : 3 page : 1 / 21 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. contents: a. physical specification .............. ....................................... p3 b. electrical specifications ................................................... p4 1. pin assignmen t ............................................................ p4 a. tft - lcd panel driving section ............... ............................ p5 b. backlight driving section ................................................. p5 2. equivalent circuit of i/o ............................................... p6 3. absolute maximum ratings .................................... .............. p6 4. electrical characteristics .................................................... p6 a. typical operating conditions ............................................. p6 b. current consumption ................................................ .... p7 c. backlight driving conditions ......................................... p7 5. ac timing ................................................................. p7 a. timing conditions ....................................................... p7 b. timin g diagram ......................................................... p8 6. dc - dc converter circuit ................................................. p9 a. boost converter ....................................................... p9 b. shutdown mode . ..................................................... p10 www.datasheet.co.kr datasheet pdf - http://www..net/
version : 3 page : 2 / 21 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. c. oscillator circuit ...................................................... p10 c. optical specifications ..................................................... p10 d. reliability test items ... .................................................... p12 e. packing form ............................................................... p13 appendix: fig1 dc - dc converter block diagram ........................................ p9 fig2 dcck block diagram .................................................... p9 fig3.pwm control state diagram ............................................. p10 fig.4 outline dimension of tft - lcd module ....................................... p14 fig.5 input signal timing relati onship ? . ........................................... p15 fig.6 input vertical timing ....................................................... p16 fig.7 horizontal input timing .................................................... p17 fig.8 hsync, vsync, da ta, dclk relationship .............................. p18 reference: fig.9 horizontal input timing (wedding clk explanation) ............ p19 fig.10 pre - filtering function timing diagram and block iagram ......... p20 fig.11 application circuit ........... ......................................... p21 www.datasheet.co.kr datasheet pdf - http://www..net/
version : 3 page : 3 / 21 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. a. physical specifications no. item specification remark 1 display resolution(dot) 280(w) ?? 2 20 (h) 2 active area(mm) 29.54(w) ?? 22.22(h) 3 screen size(inch) 1.45(diagonal) 4 dot pitch(m m) 0.1055(w) ?? 0.101(h) 5 color configuration r. g. b. delta 6 overall dimension(mm) 40.5(w) ?? 34.65(h) ?? 3.9 ( d) note 1 7 weight(g) 10 typ. 8 panel surface treatment hard coating (3h) note 1: refer to fig. 4 www.datasheet.co.kr datasheet pdf - http://www..net/
version : 3 page : 4 / 21 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. b. electrical specifications 1.pin assignment a. tft - lcd panel driving section pin no symbol i/o description remark 1 gnd - ground for logic circuit 2 v cc p supply voltage of logic control circuit for scan driver 3 v gl p negative power for scan driver 4 v gh p posi tive power for scan driver 5 frp o gate driver input signal that is fram polarity output for vcom 6 vcom i common electrode driving signal 7 drv vo power transistor gate signal for the boost converter 8 fb vi main boost regulator feedback input (fb threshold is 1.2v) 9 shl i left/right scan control input note 1 10 stb i stand by mode setting pin. note 2 11 v cc p supply voltage for digital circuit 12 shdb i shutdown input. active low. note 3 13 agnd p ground pins for analog circuits 14 vl ed i led anode 15 gled o led cathode 16 avdd p power supply for analog circuits 17 hsync i horizontal sync input. negative polarity 18 vsync i vertical sync input. negative polarity. 19 dclk i clock signal; latch data onto line latches at the rising edge. 20 d05 i data input. :msb 21 d04 i data input 22 d03 i data input 23 d02 i data input 24 d01 i data input 25 d00 i data input. :lsb 26 grb i global reset pin. note 4 www.datasheet.co.kr datasheet pdf - http://www..net/
version : 3 page : 5 / 21 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. 27 u/d i up/down scan control input note 1 28 gnd - gnd for logic circuit 29 avdd1 p supply of positive power for level shift circuit. 30 agnd1 p ground for level shift circuit i: input; o: output. vi: voltage input vo: voltage output p:power note 1: selection of scanning mode mode setting of scan control input scanning direction u/d shl note 5 normal mode l h from up to down, and from left to right. reverse mode h l from down to up, and from right to left. note 2: stand by mode(stb).if stb high, it is normal operation. if it is low, it is standb y function. normally pulled high. note 3:shutdown input(shdb).active low, dc - dc converter is off when shdb is low, normally pulled low. note 4:global reset pin. it should be connected to vcc in normal operation. if connected to gnd, the controller i s in reset state, normally pulled high. note 5 : definition of scanning direction. refer to figure as below: b. led driving section no. symbol i/o description remark pin14 vled i led anode pin 15 gled - led cathode www.datasheet.co.kr datasheet pdf - http://www..net/
version : 3 page : 6 / 21 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. 2. equivalent circuit of i/o pin no & pin name schematics 7.drv 8.fb 9 shl 10.stb 12.shdb 17.hsync 18.vsync 19.dclk 20.d07 21.d06 22.d05 23.d04 24.d03 25.d02 26.grb 27.u/d 3. absolute maxi mum ratings item symbol condition min. max. unit remark v cc gnd=0 - 0.5 5. v av dd av ss =0 - 0.5 5.5 v v gh - 0.3 21 v v gl gnd=0 - 17 0.3 v power voltage v gh ?e v gl - 38 v input signal voltage vcom - 2.9 5.2 v operating temperature topa 0 60 j ambient temperature storage temperature tstg - 25 80 j ambient temperature 4. electrical characteristics a. typical operating conditions (gnd=avss=0v) item sym bol min. typ. max. unit remark v cc i i v cc 180? www.datasheet.co.kr datasheet pdf - http://www..net/
version : 3 page : 7 / 21 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. v cc 2.5 3.3 3.6 v av dd 3.2 3.3 4.5 v v gh 15.8 17.8 19.5 v v gl ac - 5.6 - vp - p ac component of v gl. note 1 power supply v gl_h - 8.3 - 7.3 - 6.3 v high level of v gl. v cac - 5.6 - vp - p ac component, note 2 vcom v cdc - 0.4 - 0.1 0.2 v dc component, note 3 note 4 h level v oh vcc - 0.4 output signal voltage l level v ol gnd gnd+0.4 h level v ih 0.7v cc - v cc v input signal voltage l level v il gnd - 0.3v cc v drv output voltage v drv 0 vcc v drv output current idrv 10 ma feedback voltage v fb 1.2 1.25 v for dc/dc circu its. h level ioh 10 ua output current l level iol - 10 ua analog stand by current ist 200 ua dclk is stopped h level i ohf 20 ma frp output current l level i olf 20 ma for vcom circuits . note 1: the same phase and amplitude with common electrode driving signal (vcom). note 2: the brightness of lcd panel could be adjusted by the adjustment of the ac component of vcom. note 3: v cdc could be adjusted so as to minimi ze vertical straight line, flicker and maximum contrast on each module. note 4: be sure to apply gnd, v cc and v gl (v gl must lower than 0 volt) to the lcd first, and then apply v gh . note 5: the applicable pins are shl,stb,shdb,hsync,vsync,dclk,d05~d00,grb,u /d b. current consumption (gnd=avss=0v) parameter symbol condition min. typ. max. unit remark i gh v gh =17v - 0.13 0.8 m a i gl v gl _ h = - 8v - - 0.19 - 1 m a i cc v cc =3.3v - 2 4 m a current for driver i dd av dd =3.3v - 1.15 2 m a c. led driving conditions p arameter symbol min. typ. max. unit remark led current 19 20 21 ma led voltage v l 8 v led life time l l 10000 hr note 1,2 www.datasheet.co.kr datasheet pdf - http://www..net/
version : 3 page : 8 / 21 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. note 1 : ta. = 25 j , i l = 20ma note 2 : brightness to be decreased to 50% of the initial value. 5. ac timing a. timing conditions parameter symbol min. typ. max. unit. remark frequency 1/tvc 24.54 mhz high time tvch 15 ns dclk low time tvcl 15 ns rising time t r - - 10 ns note 1 falling time t f - - 10 ns note 1 60 63.56 67 us period th 156 0 dclk display period thd 49.4 us pulse width thp 1 25 dclk hsync hsync - clk timing thc 15 tc - 15 ns note 2 hsync setup time tvst 12 ns hsync hold time thhd 12 ns horizontal lines per field t v 256 262 268 t h 16.6 ms period tv 262 t h display period tvd 13.97 ms 1 dclk vsync pulse width tvp 3 th note 2 vsync setup time tvst 12 ns vsync hold time tvhd 12 ns dclk - data timing tds 10 - - ns data - clk timin g tdh 10 - - ns data d00~d05 rising time falling time tdrf - - 10 ns data set - up time tds 12 ns data hold time tdh 12 ns note 1: for all of the logic signals. note 2: display position a. . horizontal display position the display starts from the data of (269dclk, the=268dclk) as shown in f ig 4. ( the : from hsync falling edge to 1 st displayed data.) b. vertical display position parameter symbol min. typ. max. unit remark vertical display position tvs 25 th ntsc www.datasheet.co.kr datasheet pdf - http://www..net/
version : 3 page : 9 / 21 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. b. timing diagram please refer to the attached drawing, from fig. 2 to fig.5. 6. dc - dc converter circuit A015AN02 contains one high - power step - up dc - dc converter, and backplane drive circuitry for active matrix tft lcds. the output voltage of the main boost converter can be set from vcc to 13.5v with external resistor s. also included in A015AN02 are a precision 1.2v reference voltage, fault detection and logic shutdown. a .boost converter A015AN02 main boost converter uses a boost pwm architecture to produce a positive regulated voltage, please refer to the below figures to see the block diagram. fig 1 dc - dc converter block diagram in the internal architecture of dc - dc converter. the feedback voltage(vfb) will connect to the tri - angle waveform comparator ,and generates the output sign al (cp0) which determines the duty cycle for (fdc). www.datasheet.co.kr datasheet pdf - http://www..net/
version : 3 page : 10 / 21 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. fig 2 dcck block diagram to reduce the noise affect,cp0 will processed by de - bounce circuit. state - machine will generate the duty cycle by cp0 signal. to make sure that v fb can reach default vref quickly, so state - machine?s is designed as a discrete step by step function. please refer to fig 3. if cp0 is low , duty cycle will work from 0% to 75%. the maximum duty ratio is 75%. fig 3 pwm control state diagram b.shutdown mode in shutdown mode, a logic - low level on shdb, pwm controller and the reference are disabled. the supply current drops to maximize battery life and the reference is pulled to ground. every output voltage will decay. if unused , connect shdb to vcc. c.oscillator circuit the boost - converter operating frequency can be set at 1/16,1/32,1/64 times the system clock, dclk. in A015AN02?s model. the dc - dc converter osc frequency is dclk/64=383.4khz c. optical specification (note 1, note 2, note 3 ) item symbol condition min. typ. max. unit remark response time rise fall tr tf c =0 x - - 25 30 50 60 ms ms note 4 contrast ratio cr at optimized v i ewing angle 60 150 - note 5,6 viewing angle top bottom left right cr ? 10 10 30 45 45 - - - - - - - - deg . note 7 brightness y l c =0 x 160 200 - cd/m 2 note 8 www.datasheet.co.kr datasheet pdf - http://www..net/
version : 3 page : 11 / 21 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. x c =0 x 0.27 0.31 0.35 white chromaticity y c =0 x 0.29 0.35 0.40 note 1. ambient temperature =25 j . and backlight current i l =20 ma note 2. to be measured in the dark room. note 3.to be measured on the center area of panel with a field angle of 1 x by topcon luminance meter bm - 7, after 10 minutes operation. note 4. definition of response time: the output signals of photo detector are measured when the input signals are changed from ?black? to ?white?(falling time) and from ?white? to ?black?(rising time), respectively. the response time is defined as the time interval between the 10% and 90% of amplitudes. refer to figure as below. note 5. definition of contrast ratio: contr ast ratio is calculated with the following formula. photo detector output when lcd is at ?white? state photo detector output when lcd is at ?black? state note 6. white vi=v i50 ?? 1.5v black vi=v i50 ? 2.0v ? ? ? means that the analog input signal swings in phase with com signal. ? ? means that the analog input signal swings out of phase with com signal. v i50 : the analog input voltage when transmission is 50% the 100% transmission is defined as the transmission of lcd panel when all the input terminals of module are electrically opened. note 7. definition of viewing angle: signal(relative value) "black" tr tf "white" "white" 0 % 10 % 90 % 100 % contrast ratio (cr)= www.datasheet.co.kr datasheet pdf - http://www..net/
version : 3 page : 12 / 21 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. note 8. measured at the center area of the panel when all the input terminals of lcd panel are electrically opened. d. reliability tes t items: no. test items conditions remark 1 high temperature storage ta= 80 j 240h rs 2 low temperature storage ta= - 2 5 j 240h rs 3 high temperature operation ta= 60 j 240h rs 4 low temperature operation ta= 0 j 240h rs 5 high temperature and high humidit y t a= 60 j . 9 0 % rh 240h rs operation 6 heat shock - 2 5 j ~ 80 j /50 cycle 2hrs/cycle non - operation 7 electrostatic discharge ? 200v,200pf(0 [ ) , once for each terminal non - operation frequency range : 10~55hz stoke : 1.5mm sweep : 10~55hz~10hz 2 hours for each direction of x,y,z 8 vibration (6 hours for total) non - operation jis c7021, a - 10 condition a 9 mechanical shock 100 g . 6ms, ? x, ? y, ? z 3 times for each direction non - operation jis c7021, a - 7 condition c 10 vibration (with carton) random v ibration: 0.015g 2 /hz from 5~200hz ? 6db/octave from 200~500hz iec 68 - 34 11 drop (with carton) height: 60cm 1 corner, 3 edges, 6 surfaces 12 the copper?s strength for fpc the strength is larger 0.7 kg/cm ipc tm650 13 the film?s strength for fpc the stren gth is larger 0.35 kg/cm ipc tm650 www.datasheet.co.kr datasheet pdf - http://www..net/
version : 3 page : 13 / 21 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. 14 flexible ability for fpc 1. curved radius: 2mm 2. curved angle: 270 3. pulling force: 500g mit folm : diagram of test set up for folding endurance note: ta: ambient temperature. e. packing form www.datasheet.co.kr datasheet pdf - http://www..net/
version : 3 page : 14 / 21 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. |???ktapy ?a180???| epe(btm cover) epp(after) epp(right) epp(front) www.datasheet.co.kr datasheet pdf - http://www..net/
version : 3 page : 15 / 21 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. au fig.4 outline dimen sion of tft - lcd module www.datasheet.co.kr datasheet pdf - http://www..net/
version : 3 page : 16 / 21 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. fig.5 input signals timing relationship r0 g0 b0 r1 g1 b1 r2 g2 b2 r3 g3 b3 r4 g4 b4 r5 g5 b5 d0 [ 0 ?g 5 ] dclk hsync vsync ? www.datasheet.co.kr datasheet pdf - http://www..net/
version : 3 page : 17 / 21 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. vertical invalid data period dh2 dh1 dhn - 1 dhn vertical invalid data period number of v - data line 1 2 3 28 number of line tvs tv d 0.7vcc 0.3vcc tvp tv vertical sync. signal (vsync) horizontal sync. signal (hsync) dot signal (d00 - d05) fig 6 input vertical timing ? ? ? ? ? ? 90% 90% 10% 10% tr tf www.datasheet.co.kr datasheet pdf - http://www..net/
version : 3 page : 18 / 21 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. invalid data period inva lid data period d1 d2 d280 thd number of dot data r0 g0 b0 r1 g1 b1 r2 g2 tdh tds tvcl tvch tvc =1/ dclk thp thc hsync dclk d0[0;5] dclk d0 [0:5] 0.9vcc 0.1vcc tdrf fig.7 horizontal input timing) lcd valid data(280) ? ? ? ? ? 1560 dclk [ th ] the www.datasheet.co.kr datasheet pdf - http://www..net/
version : 3 page : 19 / 21 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. fig.8 hsync,vsync,data,dclk relationship www.datasheet.co.kr datasheet pdf - http://www..net/
version : 3 page : 20 / 21 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. reference: 12/13 wedding clk this period is masked ddx0 ddx1 ddx2 ddx9 ddx10 ddx11 dclk ? ? ? ? ? ? fig.9 horizontal input timing (wedding clk explanation) ddx12 ddx13 ddxn ddxn+1 data for lcd (280) lcd_ck for lcd(280 ) www.datasheet.co.kr datasheet pdf - http://www..net/
version : 3 page : 21 / 21 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. fig.10 pre - filtering function timing diagram and block diagram r0 dclk g0 b0 r1 g1 b1 r2 g2 b2 r1 g1 b1 r0 g0 b0 r1? g1? b1? r0? g0? b0? din0 din4 dinf d q d q d q d q d q pre - filtering block 2 to 1 mux din4 din0 din dclk dclk dinf pfon_in www.datasheet.co.kr datasheet pdf - http://www..net/
version : 3 page : 22 / 21 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. application circuit avdd dd6b u100 pin30 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 c113 0.1uf r119 000f c108 0.1uf shl c116 270p drv dd2b com ledgnd dd5b vglc agnd u/d stb vglc c104 1uf 3.3v +9v dd5b dd4 vgl r111 open d102 dan217u 1 2 3 1 2 3 dd6b com c106 0.1uf - frp q102 2sd1119 d100 sb07-03c avdd c105 10uf ledgnd led1 nscw215 grb dd3b c103 1uf r113 0 vgh r108 100k shdb r101 12k shdb fb r102 130k ck_out c112 0.1uf vgh c109 10uf dd2b dd7b r100 1.3k d101 ma158 l100 22uh dd7 r110 22k r114 13k avdd1 c111 10uf q101 fmmt619 vcc vr101 20k 1 3 2 gnd vr102 50k 1 3 2 c1 560p c101 0.1uf c100 0.1uf vr100 2k r122 000f dd4b dd3b agnd1 r126 000f r128 000f r109 100 u/d ledvcc dd4b c125 10uf avdd ck_out vsyncb frp d103 dan217u 1 2 3 1 2 3 vcc grb dd2 vcc c110 1uf hsync vgl r121 000f q100 fmmt619 dd7b fb stbb drv r120 000f sw hsyncb r106 10k dd5 avdd1 l102 22uh c102 0.1uf r112 10k r103 20k r124 000f led2 nscw215 stbb ledvcc agnd1 r127 000f vcc hsyncb vsyncb dclk dd6 com vglc c107 0.1uf r125 000f + r107 100k r104 2.4k r123 000f dd3 vsync shl vcc r105 30 fig 11 typical application circuit (for reference) www.datasheet.co.kr datasheet pdf - http://www..net/

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